From 37b5fcc0f76c2dcfe29abb06f8525880b5554a19 Mon Sep 17 00:00:00 2001
From: Gary Talent <gary@drinkingtea.net>
Date: Mon, 7 Jul 2025 23:36:00 -0500
Subject: [PATCH] [teagba] Put parentheses around all registers

---
 deps/teagba/include/teagba/addresses.hpp | 62 ++++++++++++------------
 1 file changed, 30 insertions(+), 32 deletions(-)

diff --git a/deps/teagba/include/teagba/addresses.hpp b/deps/teagba/include/teagba/addresses.hpp
index a8a12bc3..23380b12 100644
--- a/deps/teagba/include/teagba/addresses.hpp
+++ b/deps/teagba/include/teagba/addresses.hpp
@@ -5,50 +5,48 @@
 #pragma once
 
 #include <ox/std/array.hpp>
-#include <ox/std/span.hpp>
 #include <ox/std/units.hpp>
-#include <ox/std/types.hpp>
 
 /////////////////////////////////////////////////////////////////
 // Interrupt Handler
 
-using interrupt_handler = void (*)();
-#define REG_ISR *reinterpret_cast<interrupt_handler*>(0x0300'7FFC)
-#define REG_IE  *reinterpret_cast<volatile uint16_t*>(0x0400'0200)
-#define REG_IF  *reinterpret_cast<volatile uint16_t*>(0x0400'0202)
-#define REG_IME *reinterpret_cast<volatile uint16_t*>(0x0400'0208)
+using InterruptHandler = void(*)();
+#define REG_ISR (*reinterpret_cast<InterruptHandler*>(0x0300'7FFC))
+#define REG_IE  (*reinterpret_cast<volatile uint16_t*>(0x0400'0200))
+#define REG_IF  (*reinterpret_cast<volatile uint16_t*>(0x0400'0202))
+#define REG_IME (*reinterpret_cast<volatile uint16_t*>(0x0400'0208))
 
 /////////////////////////////////////////////////////////////////
 // Display Registers
 
-#define REG_DISPCTL  *reinterpret_cast<volatile uint32_t*>(0x0400'0000)
-#define REG_DISPSTAT *reinterpret_cast<volatile uint32_t*>(0x0400'0004)
-#define REG_VCOUNT   *reinterpret_cast<volatile uint32_t*>(0x0400'0006)
+#define REG_DISPCTL  (*reinterpret_cast<volatile uint32_t*>(0x0400'0000))
+#define REG_DISPSTAT (*reinterpret_cast<volatile uint32_t*>(0x0400'0004))
+#define REG_VCOUNT   (*reinterpret_cast<volatile uint32_t*>(0x0400'0006))
 
 /////////////////////////////////////////////////////////////////
 // Timers
 
-#define REG_TIMER0    *reinterpret_cast<volatile uint16_t*>(0x0400'0100)
-#define REG_TIMER0CTL *reinterpret_cast<volatile uint16_t*>(0x0400'0102)
+#define REG_TIMER0    (*reinterpret_cast<volatile uint16_t*>(0x0400'0100))
+#define REG_TIMER0CTL (*reinterpret_cast<volatile uint16_t*>(0x0400'0102))
 
-#define REG_TIMER1    *reinterpret_cast<volatile uint16_t*>(0x0400'0104)
-#define REG_TIMER1CTL *reinterpret_cast<volatile uint16_t*>(0x0400'0106)
+#define REG_TIMER1    (*reinterpret_cast<volatile uint16_t*>(0x0400'0104))
+#define REG_TIMER1CTL (*reinterpret_cast<volatile uint16_t*>(0x0400'0106))
 
-#define REG_TIMER2    *reinterpret_cast<volatile uint16_t*>(0x0400'0108)
-#define REG_TIMER2CTL *reinterpret_cast<volatile uint16_t*>(0x0400'010a)
+#define REG_TIMER2    (*reinterpret_cast<volatile uint16_t*>(0x0400'0108))
+#define REG_TIMER2CTL (*reinterpret_cast<volatile uint16_t*>(0x0400'010a))
 
-#define REG_TIMER3    *reinterpret_cast<volatile uint16_t*>(0x0400'010c)
-#define REG_TIMER3CTL *reinterpret_cast<volatile uint16_t*>(0x0400'010e)
+#define REG_TIMER3    (*reinterpret_cast<volatile uint16_t*>(0x0400'010c))
+#define REG_TIMER3CTL (*reinterpret_cast<volatile uint16_t*>(0x0400'010e))
 
 /////////////////////////////////////////////////////////////////
 // background registers
 
 // background control registers
 using BgCtl = uint16_t;
-#define REG_BG0CTL *reinterpret_cast<volatile BgCtl*>(0x0400'0008)
-#define REG_BG1CTL *reinterpret_cast<volatile BgCtl*>(0x0400'000a)
-#define REG_BG2CTL *reinterpret_cast<volatile BgCtl*>(0x0400'000c)
-#define REG_BG3CTL *reinterpret_cast<volatile BgCtl*>(0x0400'000e)
+#define REG_BG0CTL (*reinterpret_cast<volatile BgCtl*>(0x0400'0008))
+#define REG_BG1CTL (*reinterpret_cast<volatile BgCtl*>(0x0400'000a))
+#define REG_BG2CTL (*reinterpret_cast<volatile BgCtl*>(0x0400'000c))
+#define REG_BG3CTL (*reinterpret_cast<volatile BgCtl*>(0x0400'000e))
 
 [[nodiscard]]
 inline volatile BgCtl &regBgCtl(uintptr_t const bgIdx) noexcept {
@@ -56,10 +54,10 @@ inline volatile BgCtl &regBgCtl(uintptr_t const bgIdx) noexcept {
 }
 
 // background horizontal scrolling registers
-#define REG_BG0HOFS *reinterpret_cast<volatile uint32_t*>(0x0400'0010)
-#define REG_BG1HOFS *reinterpret_cast<volatile uint32_t*>(0x0400'0014)
-#define REG_BG2HOFS *reinterpret_cast<volatile uint32_t*>(0x0400'0018)
-#define REG_BG3HOFS *reinterpret_cast<volatile uint32_t*>(0x0400'001c)
+#define REG_BG0HOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'0010))
+#define REG_BG1HOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'0014))
+#define REG_BG2HOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'0018))
+#define REG_BG3HOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'001c))
 
 [[nodiscard]]
 volatile uint32_t &regBgHofs(auto const bgIdx) noexcept {
@@ -67,10 +65,10 @@ volatile uint32_t &regBgHofs(auto const bgIdx) noexcept {
 }
 
 // background vertical scrolling registers
-#define REG_BG0VOFS *reinterpret_cast<volatile uint32_t*>(0x0400'0012)
-#define REG_BG1VOFS *reinterpret_cast<volatile uint32_t*>(0x0400'0016)
-#define REG_BG2VOFS *reinterpret_cast<volatile uint32_t*>(0x0400'001a)
-#define REG_BG3VOFS *reinterpret_cast<volatile uint32_t*>(0x0400'001e)
+#define REG_BG0VOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'0012))
+#define REG_BG1VOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'0016))
+#define REG_BG2VOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'001a))
+#define REG_BG3VOFS (*reinterpret_cast<volatile uint32_t*>(0x0400'001e))
 
 [[nodiscard]]
 volatile uint32_t &regBgVofs(auto const bgIdx) noexcept {
@@ -80,7 +78,7 @@ volatile uint32_t &regBgVofs(auto const bgIdx) noexcept {
 /////////////////////////////////////////////////////////////////
 // User Input
 
-#define REG_GAMEPAD *reinterpret_cast<volatile uint16_t*>(0x0400'0130)
+#define REG_GAMEPAD (*reinterpret_cast<volatile uint16_t*>(0x0400'0130))
 
 /////////////////////////////////////////////////////////////////
 // Memory Addresses
@@ -89,7 +87,7 @@ volatile uint32_t &regBgVofs(auto const bgIdx) noexcept {
 
 #define MEM_IWRAM (*reinterpret_cast<ox::Array<uint8_t, 0x0300'7FFF - 0x0300'0000>*>(0x0300'0000))
 
-#define REG_BLNDCTL *reinterpret_cast<uint16_t*>(0x0400'0050)
+#define REG_BLNDCTL (*reinterpret_cast<uint16_t*>(0x0400'0050))
 
 using Palette = ox::Array<uint16_t, 128>;
 #define MEM_BG_PALETTE (*reinterpret_cast<::Palette*>(0x0500'0000))